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jNGD$4$D$0N\$D$A4$Nt&ÃD$<$D$h4$D$Mu볉t$$ MGD$I4$D$M\$D$A4$MÃD$<$D$h4$D$zM u͐t&벉t$$ qMGD$a4$D$7M\$D$A4$#MÃD$<$)D$h4$D$Lu뷉t$$ L4$&L$MzD$$$D$$$'y $ L$D$k$T@$UD$ $D$ $D$$D$KRy-'S(\$$D$$$ L\$$rIJD$$$ȇ$K$VJ$IJ$$D$$ȆK$J$ݕ$D$ג&kx.$ $D$J$$D$J$KD$ D$$jID$ $D$D$ $D$]Jp$JD$ D$$jxI$+J\$$j\ID$$D$D$ $$uJD$ D$$j!ID$ $ Z$CJD$ D$$jH$+#J\$$jHD$$D$D$ $v(1[ÐSD$ \$$D$$FD$L\$D$$DvL1[ D$ D$$FD$7LD$D$D$$DM1҅uT$ЃÍv'VS$t$ &D$ $-I$GD$$XpHt$$rIG|$ dD$ tu$1[^$-I\$F$ F$HD$$BIGf\$$YI(GD$t$$ D$D$D$G for helpPlease run READ PCI REGISTERS First!READ_HDLC_INTERRUPT_PENDING_REG: READ_DMA_INTERRUPT_PENDING_REG: RX Empty: Off=0x%X Val=0x%08X READ_DMA_DESCRIPTORS (%d T1): READ_DMA_DESCRIPTORS (%d E1): Tx Rx Read: Off=0x%X Len=%i Val=0x%08X Please specify counter number: Line:%d: Failed to write 0x%08X to offset 0x%04X (%d)! Line:%d: Failed to read from offset 0x%04X (%d)! Line:%d: Memory test failed (off 0x%04X data 0x%08X:0x%08X (%d)! Memory Test is Passed for all lines!Zero Write test failed Data=0x%x Iter=%i! 0xFF Write test failed Data=0x%X Iter=%i ! GPIO Port config test: 0,F,A,5 : PASSED!GPIO Port config test: Shift 1 : PASSED!GPIO Port config test: Shift 0 : PASSED!Control RAM Data: 0 Test Failed Data=0x%x! Control RAM Data: F Test Failed!Control RAM Data: A Test Failed!Control RAM Data: 5 Test Failed!Control RAM Data: 0,F,A,5 Test PASSED!HDLC DATA Test: 0,F,A,5 PASSED!HDLC DATA Test: Shift 0 & 1 PASSED!DMA Descr RAM Addr test Faild!DMA Descr RAM Addr test PASSED!GPIO port configuration register testRead HDLC Interrupt pending registerRead DMA Interrupt pending registerRead Control RAM (0x1000-0x1080)Specify line number (1|2|3|4) :Read DMA chain RAM (0x1800-0x1880)Read DMA status register (0x74,0x78,0x80)Read DMA descriptrs, (from 0x2000-0x22FF)Registers and Internal RAM TestsERROR: Failed to read offset 0x1040!ERROR: Failed to write to offset 0x1040!CPLD Read Offset=0x%X Data=0x%X CPLD Write Offset=0x%X Data=0x%X T1/E1/J1 Interface module (PMC based)FLASH Read Offset=0x%lX Data=0x%X FLASH Write Offset=0x%lX Data=0x%X Program FLASH Offset=0x%lX Data=0x%X Boot Flash default sector write protecte dForce to Boot from default sector activeSpecify filename (original file for verification): Failed to bind a socket to %s interface Executing cmd %s Len %i Bar %i Off %i Data 0x%x "Α2vڕdإ> O8`tkE!ݷuQ/׺]|Z?&{нf̿߿fCy#<BINHEXMCSrbread: Data file %s is empty! def_%swbread: Reading BOOT PASSED.user_%sread: Reading USER erase_sector_flash: Failed!Flash data file is too big!BOOTUSERUpdating flash (%s) %ld bytesVerification (%s) %ld bytesCan't open data file %s! Wrong HEX file format!%02x%04xWrong hex checksum value!Failed to parse HEX line! Updating flash Failed(%x) Verification Failed(%x) Updating flash Passed Verification Passedread_data_file: Can't open data file %s! read_data_file: Data file %s is empty! read_data_file: Can't allocate memory for data!read_data_file: Can't copy all data to local buffer!read: Can't open data file %s! ERROR: Failed to open file %s! ERROR: Failed to write into file!prg_flash_byte: Failed %05lX! erase_sector_flash: Sector=%d! erase_sector_flash: Sector %d (0x%05lX) PASSED! erase_sector_flash: Verification Failed to compare! %05lx -> %02x Invalid flash data file length! Updating flash Failed(%lx:%02X) Verification Failed(%lx:%02X(%02X)) Wrong HEX line length (too small)!Failed to read record-length fieldFailed to read record-addr fieldFailed to read record-type fieldFailed to read record-data field (%d) Wrong HEX line length (too long)!update: Data file is too big (%ld)! update: Programming BOOT update: Programming USER update: Verification BOOT update: Failed to compare data (%lx)! update: Verification USER Unsupported mod type %d (FXO or FXS) WRITE Failed: SPI Iface Not ReadyREAD Failed: SPI Iface Not Readyerror on iteration %d, read = %d, write was %d DAVIDY: read off:0 byte:0x%02X Module %d Failed to power up (value=0x%02X)! Module %d powered up to -%d volts (%02x) Module %d: DC-DC converter calibration done (%d:%02X)! Module %d: DC-DC converter calibration failed! Module %d: Loop current set to %dmA! ------- Direct registers (port %d) ------- ----------------------------- ------- Indirect registers (port %d) ------- Module %d PROSLIC INITIALIZATION STEP 8 %d. Reg[8] = %02X should be 0x2 %d. Reg[64] = %02X should be 0x00 %d. Reg[11] = %02X should be 0x33 %d. PROSLIC INITIALIZATION STEP 9 Indirect Registers failed to initialize on module %d. Module %d: Power leaks (value=%02X)! Module %d: Post-leakage voltage: %d volts (%02X) Module %d Timeout (value=0x%02X)! Module %d Calibration failed! Module %d: DC-DC cal has a surprising direct 107 (0x%02x)! Failed to read indirect register %d !!!!!!! %s iREG %X = %X should be %X !!!!! Init Indirect Registers UNSUCCESSFULLY.Indirect Registers failed verification.Module %d: FXO Reg 2 = %02X (should 0x3) Module %d: VoiceDAA did not bring up ISO link properly (value=%02X)! ISO-Cap is now up, line side: %02x rev %02x WARNING: REG 0x40 is set to 0x1A0 (%X) (slow SPI, 128k)!!!! Please enter module number(0 -> not sure yet) > Please enter register number > ERROR, __read_byte function returned -1Please enter the data to be written >ERROR, __write_reg function didn't return 0ERROR: %d: Invalid ID number %02X (cnt=%d) SUBSYS_ID_WORD=%X core_rev = %d Specify Module number 0-15 (dec): %d. Read FXO (chain=1) Offset=%d Data=0x%X (err=%d) %d. Write FXO (chain=1) Offset=%d Data=0x%X 1-chain mode, 0-no chain mode: %d. Read FXS (chain=%d) Offset=%d Data=0x%X (err=%d) %d. Write FXS (chain=%d) Offset=%d Data=0x%X Enable chain for all modules: Module %d: Type %s (chain %d)! Module %d (%d): Installed - Auto FXS! Module %d (%d): Installed - Auto FXO! Module %d (%d): Not installed! Module %d (%d): Failed initialize as a FXS module! Module %d (%d): Installed FXS! Module %d (%d): Failed initialize as a FXO module! Module %d (%d): Installed FXO! %d. Try ringing (chain=%d)... %d. Read FXO (chain=1) Offset=2 Data=0x%X %d. Read FXS (chain=%d) Offset=0 Data=0x%X %d. Write FXS Off=%d Data=0x%02X (%02X,cnt=%d) %d iterations completed Module %d/%d: Insane FXO Module %d/%d: Insane FXS Module %d: byte=%02X??? %3d. %02X %3d. %04X Module%d Calibration failed! Module %d Timeout! Executing SPI bus reset....VoiceDAA System: %02x Module %d: %s:%d NEWZEALANDAdjusting gainPlease enter command....=======================0. QUIT1. Reset2. Read register3. Write register4. SPI read/write test6. Set Slow SPI modePlease Select (Opt|q): scanf failedregister[%X] = %X %XRead Reg 0x40 %04x FE ready!FE not read (data=%04X)! READ FXO byte: Specify Offset (dec): WRITE FXO: READ FXS byte: WRITE FXS: Enable chain: FXOUnknownStart FXS initialization: Start FXO initialization: Ring FXS: Register dump (FXS): READ FXO byte from offset 2: READ FXS byte from offset 0: (%02X) DTMF_ROW_0_PEAKDTMF_ROW_1_PEAKDTMF_ROW2_PEAKDTMF_ROW3_PEAKDTMF_COL1_PEAKDTMF_FWD_TWISTDTMF_RVS_TWISTDTMF_ROW_RATIO_TRESDTMF_COL_RATIO_TRESDTMF_ROW_2ND_ARMDTMF_COL_2ND_ARMDTMF_PWR_MIN_TRESDTMF_OT_LIM_TRESOSC1_COEFOSC1XOSC1YOSC2_COEFOSC2XOSC2YRING_V_OFFRING_OSCRING_XRING_YPULSE_ENVELPULSE_XPULSE_YRECV_DIGITAL_GAINXMIT_DIGITAL_GAINLOOP_CLOSE_TRESRING_TRIP_TRESCOMMON_MIN_TRESCOMMON_MAX_TRESPWR_ALARM_Q1Q2PWR_ALARM_Q3Q4PWR_ALARM_Q5Q6LOOP_CLOSURE_FILTERRING_TRIP_FILTERTERM_LP_POLE_Q1Q2TERM_LP_POLE_Q3Q4TERM_LP_POLE_Q5Q6CM_BIAS_RINGINGDCDC_MIN_VDCDC_XTRALOOP_CLOSE_TRES_LOWFCCTBR21ARGENTINAAUSTRALIAAUSTRIABAHRAINBELGIUMBRAZILBULGARIACANADACHILECHINACOLUMBIACROATIACYRPUSCZECHDENMARKECUADOREGYPTELSALVADORFINLANDFRANCEGERMANYGREECEGUAMHONGKONGHUNGARYICELANDINDIAINDONESIAIRELANDISRAELITALYJAPANJORDANKAZAKHSTANKUWAITLATVIALEBANONLUXEMBOURGMACAOMALAYSIAMALTAMEXICOMOROCCONETHERLANDSNIGERIANORWAYOMANPAKISTANPERUPHILIPPINESPOLANDPORTUGALROMANIARUSSIASAUDIARABIASINGAPORESLOVAKIASLOVENIASOUTHAFRICASOUTHKOREASPAINSWEDENSWITZERLANDSYRIATAIWANTHAILANDUAEUKUSAYEMEN`j W G  R n/  c GkUWkQgkKvk7Ik33kkkk k k k l l0{)lc/l5lpx?l}ElKlVl~_l` flml yl l l l@ll6ll l!l&" m#m$-m%>m&Pm'bm(tm)@m *m+Bmmml~:mmmmmmmmmnnnnn$n,n4n:nEnMnTn\ncnhnqnynnnnnnnnnnnnnnnnnnoiooo#o,o1o=oDoMoUo\ohoro{ooooooooooooowan_init_voicedaaERROR: Line %d: Invalid address %08X Port %d: %d(%d) %d(%d) %d(%d) FR RX: %02X (%02X) %02X (%02X) %02X (%02X) %02X (%02X) %02X (%02X) %02X (%02X) %02X (%02X) FR TX: %02X (%02X) %02X (%02X) %02X (%02X) ERROR: Unsupported framer type!ERROR: Failed to read Maxim ID (%02X) %d: MAXIM Device ID Register (0x0B|0x0C|0x0D|0x0E): %02X %d: MAXIM Firmware ID Register: %02X MAXIM Read Offset=0x%X Data=0x%X %d: MAXIM Write Offset=0x%X Data=0x%X (%X) MAXIM Write Offset=0x%X Data=0x%X (%X) %d Line %d: %s: %s (lcv:%d,pcv:%d,oos:%d,e-bit:%d) Line %d: %s: %s (lcv:%d,pcv:%d,oos:%d) Line %d: %s: GREEN (lcv:%d,pcv:%d,oos:%d,e-bit:%d) Line %d: %s: GREEN (lcv:%d,pcv:%d,oos:%d) Specify T1 Line number (1-%d): ERROR: Failed to read Device IDSpecify Recory Clock Line (0-for master): Line %d: Dummy T1 configuration Specify E1 Line number (1-%d): Line %d: Dummy E1 configuration ********************************************** Port %d: Receive Framer Registers:Port %d: Transmit Framer Registers:Specify T1/E1 Line number (1-%d): LIU : %02X (%02X) BERT : %02X (%02X) J1T1E156KDS3E3FXO/FXSConfiguring %d %s: 0db7.5db15dB22.5dB0-110ft110-220ft220-330ft330-440ft440-550ft550-660ft0-133ft133-266ft266-399ft399-533ft533-599ft120OH75OHNormalMasterESFD4non-CRC4UnframedG.751G.832C-bitM13AMIB8ZSHDB3B3ZS %s, %s, %s, %s %s, %s, %s ERROR: Unsupported line code!Device is DS26528!Device is DS26524!Device is DS26522!Device is DS26521!Reset setReset ClearSpecify Line number (1-%d): ConfiguredNot configuredLine %d: Set to T1 mode (%s) Line %d: Set to E1 mode (%s) Set MAXIM framer Reset!MAXIM READ: MAXIM WRITE: ERROR: Invalid media type!Press any key to updatemaxim_reg_%d.txtwERROR: Failed to open file!Port %d: Global Registers: %04X: Port %d: LIU Registers:Port %d: BERT Registers:%d: 0xFC: %02X (%02X) %d: register test finished! Press ENTER to set reset.Press ENTER to clear reset.Id1 = 0x%X Id2 = 0x%X Enter Offset in HEX format.Offset[%X] = 0x%X Enter value in HEX format.k k !!!k ! """!!4#7//!0?0i01 23G$?'g*-.W7464=j>>G?y?>>MAXIM CPLD READ: MAXIM CPLD WRITE: MAXIM CPLD Read Offset=0x%X Data=0x%X MAXIM CPLD Write Offset=0x%X Data=0x%X Number of times to run test: Len must be 1|2|4Memory data bus test failedaddress:%x, len:%d pattern:%x repeat:%d of %d DMA Chain RAM test Memory data bus test passed (off:%x, len:%d, repeat:%d)   (GoH4t k  @@(ooo@·އ.>N^n~Έވ.>N^n~ΉމiOnO&N Xilinx: Setup Chip Configuration -------------------------------- 1. Read and display configuration file 2. Change parameters 3. Chip setup q. Quit Please Select (|q): Xilinx: Registers and Internal Ram Tests ---------------------------------------- 1. GPIO port configuration register test (0x44) 2. Control RAM address test 3. Control RAM data test 4. HDLC address test (for all 32 channels) 5. HDLC data test (for all 32 channels) 6. DMA descr RAM address test 7. DMA descr RAM data test 8. Access test on Reg 0x40 q. Quit Please Select (|q): Xilinx: Read Chip Control ------------------------- 1. Read PCI registers (00-10,3C) 2. Read Chip configuration (40,48) 3. Read HDLC Interrupt pending register 4. Read DMA Interrupt pending register 5. Read Control RAM (0x1000-0x1080) 6. Read DMA chain RAM register (0x1800-1880) 7. Read DMA status register (0x74,0x78,0x80) 8. Read DMA descriptors, (from 0x2000-0x22FF) 9. LED Test 10. Reset HDLC 11. Reset Chip 12. Read (8/16/32) from offset 13. Write (8/16/32) from offset 14. Memory Test (0x2000-0x3FFF) 15. Restore PCI Registers q. Quit Please Select (|q): Xilinx - A600: Main Menu ----------------- 0. Disable Global Chip/FrontEnd/CPLD Reset 1. Read Chip Control and Status 2. Registers and Internal RAM Tests 3. Setup chip configuration 4. Reload PCI Bios Info 5. CPLD Initialization 6. Analog, FXO/FXS board 7. Maxim Initialization 8. Maxim CPLD Access 9. Memory Test 10.Flash Update q. Quit Please Select (|q): Xilinx: CPLD Configuration ------------------------------ 1. Read CPLD Access. 2. Write CPLD Access. 3. LED Test. 4. Read Front End Type. 5. Boot Flash read. 6. Boot Flash write. 7. Check Flash ID. 8. Update Flash code (Default sector) 9. Update Flash code (User sector) 10. Reset Flash. 11. Default Flash sector Erase ! 12. User Flash sector Erase ! 13. Chip Erase ! 14. Program Flash (byte). 15. Default sector verification. 16. User sector verification. 17. Read Board Status. 18. Reboot Xilinx from the Flash Default sector. 19. Reboot Xilinx from the Flash User sector. 20. Program Flash Full. 21. Read and Save Default/User sector into file. q. Quit. Please Select (Opt|q): Usage: args: -i -c [READ|WRITE|RXDMA|TXDMA] -bar [0|1] -off -l [1|2|4|X] -d ./aft_test -i whdlc0 -cmd READ -bar 0 -off 10 -l 1 ./aft_test -i whdlc0 -cmd WRITE -bar 0 -off 10 -l 4 -d 0x80000000      ??@`      Xilinx: Analog Configuration ------------------------------ 1. Chip init. 2. SPI Bus Reset. 3. Read FXO byte. 4. Write FXO byte. 5. Read FXS byte. 6. Write FXS byte. 7. Enable chain. 8. Enable chain for all modules. 9. Print chain status. 10. Auto init. 11. FXS init. 12. FXO init. 13. Ring FXS. 14. Tones FXS. 15. Regdump (FXS). 16. Read FXO byte from each module (offset 2). 17. Read FXS byte from each module (offset 0). 18. Write & Verify byte to FXS module. 19. Work with Remora Tester. q. Quit. Please Select (Opt|q): 102d Debug Menu ---------------- 0. Toggle Reset Pin. 1. Read Id of Framer #1. 2. Read Id of Framer #2. 3. Read Dallas 1 Register. 4. Write Dallas 1 Register. 5. Read Dallas 2 Register. 6. Write Dallas 2 Register. 7. Test data bus. Please select(q to quit) Xilinx: Maxim Configuration (%s) ------------------------------ 1. Set T1 parameters 2. Set E1 parameters 3. Print current settings 4. Clear Reset MAXIM framer (CPLD) 5. Set Reset MAXIM framer (CPLD) 6. Read Device ID Register 7. Read MAXIM Access 8. Write MAXIM Acess 9. Config MAXIM chip 10. Read MAXIM Status (Led) 11. Sample T1 Maxim configuration 12. Sample E1 Maxim configuration 13. Read register dump 14. Check interrupts 15. Clear interrupts 17. Clear Global T1/E1 reset 18. Set global T1/E1 reset q. Quit Please Select (Opt|q):  Xilinx: Maxim CPLD Configuration ------------------------------ 1. Read MAXIM CPLD Access 2. Write MAXIM CPLD Acess q. Quit Please Select (Opt|q): Memory Test Menu ---------------- 0. DMA Chain RAM test. 1. DMA Descriptor RAM test. Please select(q to quit) Memory Test Menu ---------------- 0. Line 0. 1. Line 1. Please select(q to quit)GCC: (GNU) 4.1.1 20070105 (Red Hat 4.1.1-52)GCC: (GNU) 4.1.1 20070105 (Red Hat 4.1.1-52)GCC: (GNU) 4.1.2 20071124 (Red Hat 4.1.2-42)GCC: (GNU) 4.1.2 20071124 (Red Hat 4.1.2-42)GCC: (GNU) 4.1.2 20071124 (Red Hat 4.1.2-42)GCC: (GNU) 4.1.2 20071124 (Red Hat 4.1.2-42)GCC: (GNU) 4.1.2 20071124 (Red Hat 4.1.2-42)GCC: (GNU) 4.1.2 20071124 (Red Hat 4.1.2-42)GCC: (GNU) 4.1.2 20071124 (Red Hat 4.1.2-42)GCC: (GNU) 4.1.2 20071124 (Red Hat 4.1.2-42)GCC: (GNU) 4.1.1 20070105 (Red Hat 4.1.1-52).symtab.strtab.shstrtab.interp.note.ABI-tag.gnu.hash.dynsym.dynstr.gnu.version.gnu.version_r.rel.dyn.rel.plt.init.text.fini.rodata.eh_frame.ctors.dtors.jcr.dynamic.got.got.plt.data.bss.comment#(( 1oHH,; ttC44kKoXXo0g ((p @@@ yt00 (G(`G`A (( ,, 44 << @@     8  0% _ 3 (Ht4(@   0 (G `G(,4<@ T ,*48<ES b x 0(<G `H {+@7E@ Sp \@ ox@  P @* ( `p@p 01 p  _ )00 3` G0x a^ n  0Y # r  $  `"   l@)$ /CUeV s,, ,,,,$@- 8T _4rPCI }  ж- F D 0 BX @`8  k `  3`G:gL(G R}d=L t @   qCE\+P <Pj dp- k`q >dG O A ` ?/<ApB Vbs @@V 7 'p% 2D А%  'E :hGG U?Q f r"8Fi  9< p<  p  o. _@  W Ў) ` y | $ p    Y ` Cg    * 0#S ? 0K J \  z P @    E P   4  - 4 W ?  W %i  z   w - F 0 T     call_gmon_startcrtstuff.c__CTOR_LIST____DTOR_LIST____JCR_LIST__dtor_idx.5790completed.5788__do_global_dtors_auxframe_dummy__CTOR_END____FRAME_END____JCR_END____do_global_ctors_auxxilinx_test.cusage_infote1_linereg_internal_ram_testsread_chip_controlset_chip_configmain_menu_listcpld_configxilinx_cpld.cget_file_typefilesizeread_bin_data_fileflash_idaft_flash_bin_fileaft_flash_hex_fileverify_flash_dataxilinx_analog.ctranslate_3215indirect_regs__write_bytewrite_bytewan_proslic_write_indirect__read_bytechain_enableread_bytewan_powerup_proslicwan_proslic_read_indirectread_regdumpwan_init_proslicspi_bus_resetwan_init_voicedaafxo_modes__FUNCTION__.5335analog_configxilinx_maxim.cfe_idintr_ctrlte_configcheck_id_regmax_port_numreset.5484maxim_configdebug_menuxilinx_maxim_cpld.cmaxim_cpld_configxilinx_memory.cmemory_test_dma_line_select_menumemory_test_main_menu__preinit_array_start__fini_array_end_GLOBAL_OFFSET_TABLE___preinit_array_end__fini_array_start__init_array_end__init_array_start_DYNAMICdata_start__errno_location@@GLIBC_2.0read_maximsprintf@@GLIBC_2.0get_repeatcheck_flash_idhit_any_keycore_rev__libc_csu_finixilinx_memory_test_dma_descriptor_startget_line_offsetsockmain_menucpld_set_clockapi_cmd__gmon_start___Jv_RegisterClasses_fp_hwstrchr@@GLIBC_2.0_finisystem@@GLIBC_2.0debug_102d_menuputchar@@GLIBC_2.0analog_interfacemaxim_cpld_accessexec_fe_write_cmdflash_specfgets@@GLIBC_2.0memset@@GLIBC_2.0__strtol_internal@@GLIBC_2.0i_name__libc_start_main@@GLIBC_2.0exec_fe_read_cmd_IO_getc@@GLIBC_2.0exec_reload_pci_cmdverifyflagsread_write_test2perror@@GLIBC_2.0usleep@@GLIBC_2.0global_pci_regs_set_IO_stdin_usedread_cpldfree@@GLIBC_2.0scanf@@GLIBC_2.0__data_startchain_ctrlfflush@@GLIBC_2.0ioctl@@GLIBC_2.0socket@@GLIBC_2.0memory_data_bus_testmodule_listfseek@@GLIBC_2.0fclose@@GLIBC_2.1exec_read_cmdread_maxim_cpldMakeConnectionmemcpy@@GLIBC_2.0strlen@@GLIBC_2.0write_dallas_1fopen@@GLIBC_2.1xilinx_memory_test_dma_chainexec_commandupdatexilinx_memory_test__dso_handleread_dallas_1write_maxim_cpldwrite_maximfeof@@GLIBC_2.0strcpy@@GLIBC_2.0ftell@@GLIBC_2.0__DTOR_END____libc_csu_initsetup_chip_configuration_menuprintf@@GLIBC_2.0bind@@GLIBC_2.0arg_error_checkread_flashclose@@GLIBC_2.0fwrite@@GLIBC_2.0read_chip_control_menuled_testread_remora_tester_registerfprintf@@GLIBC_2.0global_pci_regs__bss_startmalloc@@GLIBC_2.0exec_write_cmderase_sector_flashwrite_dallas_2get_rw_sizefputc@@GLIBC_2.0read_dallas_2stdin@@GLIBC_2.0maxim_initializationwrite_cpldoctasic_fast_testregisters_and_internal_ram_test_menustrncasecmp@@GLIBC_2.0chip_erasefe_cfg_endstdout@@GLIBC_2.0puts@@GLIBC_2.0__strtoul_internal@@GLIBC_2.0write_flashusagesscanf@@GLIBC_2.0cmd_listfread@@GLIBC_2.0_edataupdate_ledwork_with_remora_testerstrcmp@@GLIBC_2.0exec_octasic_cmdconvert_maxim_regexit@@GLIBC_2.0write_remora_tester_registerreset_flash__i686.get_pc_thunk.bxupdate_manmain_initprg_flash_byteread_man